InhaltsangabeGaAs electronic devices.- Deep submicron dry etching.- Characterization of hot carrier trapping in the gate oxide of MOSFETs.- The use of boron doped polysilicon in PMOS devices.- Semiconductor device fabrication with high energy ion implantation.- A self-aligned gate definition process with sub-micron gaps.- Novel submicron processes for shallow p+-n junctions.- Enhanced process window for BPSG flow in a salicide process using an LPCVD nitride cap layer.- Silicon oxidation rate dependence on dopant pile-up.- Beryllium and manganese diffusion in Ga0.47In0.53As during MBE-growth.- Quality and applications of In(Ga)AIAs-layers.- On the high-frequency behaviour of ohmic contacts.- Assessment of semi-insulating InP:Fe layers for substrate applications.- Investigation on p-buried GaAs MESFETs.- An InGaAs/GaAs strained superlattice MSM photodiode for fast light detection at 1.3?m.- Scaling-down of submicrometer GaAs MESFETs.- The mobility model in MINIMOS.- MESFET analysis with MINIMOS.- Numerical analysis of breakdown in silicon diodes.- A new algorithm to accelerate convergence in the simulation of semiconductor devices.- Narrow-width effects in submicron MOS ICs.- Simulation of parasitic currents and other effects in narrow channel devices.- 3D simulation of parasitic effects in EPROM cells.- Requirements for device and process modelling of submicron devices.- Geometry dependent bird's beak formation for submicron LOCOS isolation.- Combination of LOCOS and BOX isolation for submicron CMOS technology.- Impact of oxide thinning at the LOCOS edge of MOS capacitors on constant current stress.- A self-aligned isolation oxide process before gate formation for enhanced packing density of megabit DRAMs.- Field isolation using shallow trenches for submicron CMOStechnology.- High performance submicron SILO process for high density EPROM memories using rapid thermal nitridation of silicon.- High speed BICMOS technology with emitter-base self-aligned structure.- Ohmic contacts to n-type GaAs using GeMoW metallization for self aligned processing.- Reliable, high temperature stable Schottky contacts to GaAs based on LaB6 diffusion barriers.- GaAs/InAs heterostructures grown by atomic layer epitaxy.- High temperature LPCVD of dielectrics on III-V substrates for device application.- Short-time diffusion of zinc into InP and InGaAsP from spin-on films.- Schottky barrier enhanoement on InP using pseudomorphic GaInP MBE layers.- Control of the Si3N4 InGaAs interfaces by constant capacitance transients.- Simulation of ion implantation into multilayer structures.- Simulation of the lateral spread of implanted ions: experiments.- The modeling and simulation of reactive ion etching rate using statistical method.- Two-dimensional aspects of ion enhanced reactive etching of silicon with SF6.- A yield modelling system for NMOS and CMOS IC.- Calculation of bipolar transistor base resistance using finite element method.- Efficient integration of device and circuit simulation.- Dopant activation and defect annihilation of heavily doped arsenic implanted silicon layers.- Self-aligned CoSi2 in a submicron CMOS process.- Reduction of titanium silicide degradation during boro-phosphosilicate glass reflow.- Shallow junctions fabrication by using molibdenum silicide and rapid thermal annealing.- A study of ultra shallow junctions by diffusion from self-aligned silicides.- The outdiffusion of boron and arsenic from pre-formed cobalt disilicide layers.- Ion-beam mixed MoSi2 layers: formation and contact properties.- An investigation into the parasitic effects affecting the operation of HEMT-based ICs.- Automated measurement of the bias dependence of low frequency small-signal parameter dispersions in GaAs MESFETs.- High speed Ga0.47In0.53As MISFETs grown by metal organic vapor phase epitaxy.- A resonant tunneling high electron mobility transistor.- Implanted-collector InGaAsP/InP heterojunction bipolar transistor.- 0.25 ?m all level e-beam pseudomorphic AIGaAs/lnGaA